1. Field of the Invention
The invention relates to the field of semiconductor memories and in particular to memory cores for read only memories (ROM, EPROM) or flash memories (EEPROM). Specifically, the invention relates to improvements in a method of precharging a memory core, sensing of the data lines in a memory core, and address decoding of the memory core.
2. Description of the Prior Art
Grounded Memory Core Design and Methodology
Architectures for very large scale integrated (VLSI) ROMs using virtual ground lines and diffusion bits lines to access banks of core cells are well known. Descriptions of such architectures can be found in Okada, et.al. "18 Mb ROM Design Using Bank Select Architecture," Integrated Circuits Group, Sharp Corp. However, such architectures are subject to several limitations and drawbacks as a discussed in the parent applications of this application and as are implicitly further detailed in the brief summary below wherein the improvements of the invention of the prior art and over the art of the parent application are explained.
Differential Sense Amplifier
Although not prior art, the parent application shows a sense amplifier approach using a current mirror. A schematic drawing of this previous sense amplifier is presented in FIG. 21 of the parent, which is reproduced here as FIG. 5, since many of the improvements of the invention are best understood in comparison to the design in the parent application.
Both approaches use the same clocking signals and have the same timing. Also, both approaches amplify voltage differences of about 0.15 volts. The previous design amplifies voltages that are close to 2.0 volts with differences of about 0.15 volts.
The current mirror approach used in the previous design loads the differential amplifier output nodes with an unbalanced capacitive load. This unbalanced load favors one side of the latch over the other side of the latch. It would be possible to add capacitance to the previous design to balanced the nodes, but extra capacitance slows the latch and reduces the transient response of the latch.
Because of the small difference in voltages being sensed, small imbalances in the previous design of the differential amplifier may have a large enough effect to cause the differential amplifier to fall into the wrong state.
Virtual Ground and Bit Line Decoder
A design for a virtual ground and bit line decoder is described in the copending parent application in connection with FIGS. 18-20 (N387). Another design for a virtual ground and bit line decoder is shown in copending application N051-D in connection with FIGS. 1-2.
A previous interlock method was used in the CMOS 4 Megabyte ROM circuit. A schematic diagram of a previous interlock method is presented in FIG. 8.
The designs in the parent application both show approaches to decoding virtual ground lines and bit lines in a ROM. These previous decoder circuits are similar to the present decoder circuit, but the methods of decoding are different as will be described below.
The interlock method shown in FIG. 8 is an example of a previous interlock method. The present interlock method is an improvement of this design.